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general description the max6715?ax6729 are ultra-low-voltage microproces- sor (?) supervisory circuits designed to monitor two or three system power-supply voltages. these devices assert a sys- tem reset if any monitored supply falls below its factory- trimmed or adjustable threshold and maintain reset for a minimum timeout period after all supplies rise above their thresholds. the integrated dual/triple supervisory circuits sig- nificantly improve system reliability and reduce size com- pared to separate ics or discrete components. these devices monitor primary supply voltages (v cc 1) from 1.8v to 5.0v and secondary supply voltages (v cc 2) from 0.9v to 3.3v with factory-trimmed reset threshold voltage options (see reset voltage threshold suffix guide ). an externally adjustable rstin input option allows customers to monitor a third supply voltage down to 0.62v. these devices are guaranteed to be in the correct reset output logic state when either v cc 1 or v cc 2 remains greater than 0.8v. a variety of push-pull or open-drain reset outputs along with watchdog input, manual reset input, and power-fail input/out- put features are available (see selector guide ). select reset timeout periods from 1.1ms to 1120ms (min) (see reset timeout period suffix guide ). the max6715?ax6729 are available in small 5, 6, and 8-pin sot23 packages and oper- ate over the -40? to +85? temperature range. applications multivoltage systems telecom/networking equipment computers/servers portable/battery-operated equipment industrial equipment printer/fax set-top boxes features v cc 1 (primary supply) reset threshold voltages from 1.58v to 4.63v v cc 2 (secondary supply) reset threshold voltages from 0.79v to 3.08v externally adjustable rstin threshold for auxiliary/triple-voltage monitoring (0.62v internal reference) watchdog timer option 35s (min) long startup period 1.12s (min) normal timeout period manual reset input option power-fail input/power-fail output option (push-pull and open-drain active-low) guaranteed reset valid down to v cc 1 or v cc 2 = 0.8v reset output logic options immune to short v cc transients low supply current 14? (typ) at 3.6v small 5, 6, and 8-pin sot23 packages max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits ________________________________________________________________ maxim integrated products 1 ordering information in out2 out1 dc/dc converter unregulated dc r1 r2 v cc 1v cc 2 rstin/pfi mr rst wdi pfo max67_ _ pushbutton switch i/o supply core supply reset i/o nmi p 1.8v 0.9v typical operating circuit 19-2325; rev 2; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. selector guide appears at end of data sheet. part temp range pin-package max6715 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6716 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6717 uk_ _d_ -t -40 c to +85 c 5 sot23-5 max6718 uk_ _d_ -t -40 c to +85 c 5 sot23-5 max6719 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6720 ut_ _d_ -t -40 c to +85 c 6 sot23-6 note: the first ? _?are placeholders for the threshold voltage levels of the devices. desired threshold levels are set by the part number suffix found in the reset voltage threshold suffix guide. the ??after the d is a placeholder for the reset timeout delay time. desired delay time is set using the timeout period suffix found in the reset timeout period suffix guide. for example the max6716utltd3-t is a dual-voltage supervisor v th 1 = 4.625v, v th 2 = 3.075v, and 210ms (typ) timeout period. ordering information continued at end of data sheet.
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc 1 = v cc 2 = 0.8v to 5.5v, gnd = 0, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc 1, v cc 2 ..........................................................-0.3v to +6v open-drain rst , rst1 , rst2 , pfo , rst ................-0.3v to +6v push-pull rst, rst1 , pfo , rst ...............-0.3v to (v cc 1 + 0.3v) push-pull rst2 .........................................-0.3v to (v cc 2 + 0.3v) rstin, pfi, mr , wdi ................................................-0.3v to +6v input current/output current (all pins) ...............................20ma continuous power dissipation (t a = +70 c) 5-pin sot23-5 (derate 7.1mw/ c above +70 c) ........571mw 6-pin sot23-6 (derate 8.7mw/ c above +70 c) ........696mw 8-pin sot23-8 (derate 8.9mw/ c above +70 c) ........714mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units supply voltage v cc 0.8 5.5 v v cc 1 < 5.5v, all i/o pins open 15 39 i cc1 v cc 1 < 3.6v, all i/o pins open 10 28 v cc 2 < 3.6v, all i/o pins open 4 11 supply current i cc2 v cc 2 < 2.75v, all i/o pins open 3 9 a l (falling) 4.500 4.625 4.750 m (falling) 4.250 4.375 4.500 t (falling) 3.000 3.075 3.150 s (falling) 2.850 2.925 3.000 r (falling) 2.550 2.625 2.700 z (falling) 2.250 2.313 2.375 y (falling) 2.125 2.188 2.250 w (falling) 1.620 1.665 1.710 v cc 1 reset threshold v th1 v (falling) 1.530 1.575 1.620 v t (falling) 3.000 3.075 3.150 s (falling) 2.850 2.925 3.000 r (falling) 2.550 2.625 2.700 z (falling) 2.250 2.313 2.375 y (falling) 2.125 2.188 2.250 w (falling) 1.620 1.665 1.710 v (falling) 1.530 1.575 1.620 i (falling) 1.350 1.388 1.425 h (falling) 1.275 1.313 1.350 g (falling) 1.080 1.110 1.140 f (falling) 1.020 1.050 1.080 e (falling) 0.810 0.833 0.855 v cc 2 reset threshold v th2 d (falling) 0.765 0.788 0.810 v reset threshold tempco 20 ppm/ c reset threshold hysteresis v hyst referenced to v th typical 0.5 %
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc 1 = v cc 2 = 0.8v to 5.5v, gnd = 0, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units v cc to reset output delay t rd v c c 1 = ( v th 1 + 100m v ) to ( v th 1 - 100m v ) or v c c 2 = ( v th 2 + 75m v ) to ( v th 2 - 75m v ) 20 s d1 1.1 1.65 2.2 d2 8.8 13.2 17.6 d3 140 210 280 d5 280 420 560 d6 560 840 1120 reset timeout period t rp d4 1120 1680 2240 ms adjustable reset comparator input (max6719/max6720/max6723?ax6727) rstin input threshold v rstin 611 626.5 642 mv rstin input current i rstin -25 +25 na rstin hysteresis 3mv rstin to reset output delay t rstind v rstin to (v rstin - 30mv) 22 ? power-fail input (max6728/max6729) pfi input threshold v pfi 611 626.5 642 mv pfi input current i pfi -25 +25 na pfi hysteresis v pfh 3mv pfi to pfo delay t dpf (v pfi + 30mv) to (v pfi - 30mv) 2 s manual reset input (max6715?ax6722/max6725?ax6729) v il 0.3 ? v cc 1 mr input voltage v ih 0.7 ? v cc 1 v mr minimum pulse width 1s mr glitch rejection 100 ns mr to reset delay t mr 200 ns mr pullup resistance 25 50 80 k ? watchdog input (max6721?ax6729) first watchdog period after reset timeout period 35 54 72 watchdog timeout period t wd normal mode 1.12 1.68 2.24 s wdi pulse width t wdi (note 2) 50 ns v il 0.3 ? v cc 1 wdi input voltage v ih 0.7 ? v cc 1 v wdi input current i wdi wdi = 0 or v cc 1-1+1a
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 4 _______________________________________________________________________________________ note 1: devices tested at +25 c. overtemperature limits are guaranteed by design and not production tested. note 2: parameter guaranteed by design. electrical characteristics (continued) (v cc 1 = v cc 2 = 0.8v to 5.5v, gnd = 0, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units reset/power-fail outputs v cc 1 or v cc 2 0.8v, i sink = 1a, output asserted 0.3 v cc 1 or v cc 2 1.0v, i sink = 50a, output asserted 0.3 v cc 1 or v cc 2 1.2v, i sink = 100a, output asserted 0.3 v cc 1 or v cc 2 2.7v, i sink = 1.2ma, output asserted 0.3 rst / rst1 / rst2 / pfo output low (push-pull or open-drain) v ol v cc 1 or v cc 2 4.5v, i sink = 3.2ma, output asserted 0.4 v v cc 1 1.8v, i source = 200a, output not asserted 0.8 ? v cc 1 v cc 1 2.7v, i source = 500a, output not asserted 0.8 ? v cc 1 rst / rst1 / pfo output high (push-pull only) v oh v cc 1 4.5v, i source = 800a, output not asserted 0.8 ? v cc 1 v v cc 2 1.8v, i source = 200a, output not asserted 0.8 ? v cc 2 v cc 2 2.7v, i source = 500a, output not asserted 0.8 ? v cc 2 rst2 output high (push-pull only) v oh v cc 2 4.5v, i source = 800a, output not asserted 0.8 ? v cc 2 v v cc 1 1.0v, i source = 1a, reset asserted 0.8 ? v cc 1 v cc 1 1.8v, i source = 150a, reset asserted 0.8 ? v cc 1 v cc 1 2.7v, i source = 500a, reset asserted 0.8 ? v cc 1 rst output high (push-pull only) v oh v cc 1 4.5v, i source = 800a, reset asserted 0.8 ? v cc 1 v v cc 1 or v cc 2 1.8v, i sink = 500a, reset not asserted 0.3 v cc 1 or v cc 2 2.7v, i sink = 1.2ma, reset not asserted 0.3 rst output low (push-pull or open drain) v ol v cc 1 or v cc 2 4.5v, i sink = 3.2ma, reset not asserted 0.4 v rst / rst1 / rst2 / pfo output open-drain leakage current output not asserted 0.5 a rst output open-drain leakage current output asserted 0.5 a
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits _______________________________________________________________________________________ 5 0 4 2 10 8 6 16 14 12 18 -40 10 -15 35 60 85 supply current vs. temperature v cc 1 = 5v, v cc 2 = 3.3v max6715-29 toc01 temperature ( c) supply current ( a) total i cc 1 i cc 2 0 4 2 10 8 6 16 14 12 18 -40 10 -15 35 60 85 supply current vs. temperature v cc 1 = 3.3v, v cc 2 = 2.5v max6715-29 toc02 temperature ( c) supply current ( a) total i cc 1 i cc 2 0 4 2 10 8 6 16 14 12 18 -40 10 -15 35 60 85 supply current vs. temperature v cc 1 = 2.5v, v cc 2 = 1.8v max6715-29 toc03 temperature ( c) supply current ( a) total i cc 1 i cc 2 0 4 2 10 8 6 16 14 12 18 -40 10 -15 35 60 85 supply current vs. temperature v cc 1 = 1.8v, v cc 2 = 1.2v max6715-29 toc04 temperature ( c) supply current ( a) total i cc 1 i cc 2 0.998 1.000 0.999 1.003 1.002 1.001 1.006 1.005 1.004 1.007 -40 10 -15 35 60 85 normalized reset/watchdog timeout period vs. temperature max6715-29 toc05 temperature ( c) reset/watchdog period 10,000 1000 100 10 1 100 10 1000 maximum v cc transient duration vs. reset threshold overdrive max6715-29 toc06 reset threshold overdrive (mv) maximum v cc transient duration ( s) reset occurs above this line 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 -40 -15 10 35 60 85 normalized v cc reset threshold vs. temperature max6715-29 toc07 temperature ( c) reset threshold 625 627 626 629 628 630 631 -40 85 reset input and power-fail input threshold vs. temperature max6715-29 toc08 temperature ( c) threshold (mv) 10 -15 35 60 44 47 46 45 48 49 50 51 52 53 54 -40 10 -15 35 60 85 v cc to reset delay vs. temperature max6715-29 toc09 temperature ( c) v cc to reset delay ( s) 100mv overdrive typical operating characteristics (v cc 1 = 5v, v cc 2 = 3.3v, t a = +25 c, unless otherwise noted.)
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 6 _______________________________________________________________________________________ pin description 22.8 23.0 23.2 23.4 23.6 23.8 24.0 24.2 24.4 -40 -15 10 35 60 85 reset input to reset output delay vs. temperature max6715-29 toc10 temperature ( c) rstin to reset delay ( s) 30mv overdrive 2.0 2.1 2.2 2.4 2.3 -40 10 -15 35 60 85 power-fail input to power-fail output delay vs. temperature max6715-29 toc11 temperature ( c) rstin to reset delay ( s) 30mv overdrive 0 0 v rst 2v/div max6715-29 toc12 50ns/div mr to reset output delay v mr 2v/div typical operating characteristics (continued) (v cc 1 = 5v, v cc 2 = 3.3v, t a = +25 c, unless otherwise noted.) pin max6715/ max6716 max6717/ max6718 max6719/ max6720 max6721/ max6722 max6723/ max6724 max6725/ max6726 max6727 max6728/ max6729 name function 1111111, 41 rst / rst1 active-low reset output, open-drain or push-pull. rst/rst1 changes from high to low when v cc 1 or v cc 2 drops below the selected reset thresholds, rstin is below threshold, mr is pulled low, or the watchdog triggers a reset. rst/rst1 remains low for the reset timeout period after v cc 1/ v cc 2/rstin exceed the device reset thresholds, mr goes low to high, or the watchdog triggers a reset. open-drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1.
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits _______________________________________________________________________________________ 7 pin description (continued) pin max6715/ max6716 max6717/ max6718 max6719/ max6720 max6721/ max6722 max6723/ max6724 max6725/ max6726 max6727 max6728/ max6729 name function 5 rst2 active-low reset output, open-drain or push-pull. rst2 changes from high to low when v cc 1 or v cc 2 drops below the selected reset thresholds or mr is pulled low. rst2 remains low for the reset timeout period after v cc 1/v cc 2 exceed the device reset thresholds or mr goes low to high. open-drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 2. 22222222 gnd ground 3333 555 mr active-low manual reset input. internal 50k ? pullup to v cc 1. pull low to force a reset. reset remains active as long as mr is low and for the reset timeout period after mr goes high. leave unconnected or connect to v cc 1 if unused. 44444666 v cc 2 secondary supply voltage input. powers the device when it is above v cc 1 and input for secondary reset threshold monitor. 65666888 v cc 1 primary supply voltage input. powers the device when it is above v cc 2 and input for primary reset threshold monitor.
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 8 _______________________________________________________________________________________ pin description (continued) pin max6715/ max6716 max6717/ max6718 max6719/ max6720 max6721/ max6722 max6723/ max6724 max6725/ max6726 max6727 max6728/ max6729 name function 53333 wdi watchdog input. if wdi remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and the reset output asserts for the reset timeout period. the internal watchdog timer clears whenever a reset is asserted or wdi sees a rising or falling edge. the watchdog has a long timeout period (35s min) after each reset event and a short timeout period (1.12s min) after the first valid wdi transition. leave wdi floating to disable the watchdog timer function. 5 577 rstin undervoltage reset comparator input. high- impedance input for adjustable reset monitor. the reset output is asserted when rstin falls below the 0.626v internal reference voltage. set the monitored voltage reset threshold with an external resistor-divider network. connect rstin to v cc 1 or v cc 2 if not used. 7 pfi power-fail voltage monitor input. high- impedance input for internal power-fail monitor comparator. connect pfi to an external resistor- divider network to set the power-fail threshold voltage (0.626v typical internal reference voltage). connect to gnd, v cc 1, or v cc 2 if not used.
detailed description supply voltages the max6715 max6729 microprocessor (p) supervi- sory circuits maintain system integrity by alerting the p to fault conditions. these ics are optimized for systems that monitor two or three supply voltages. the output- reset state is guaranteed to remain valid while either v cc 1 or v cc 2 is above 0.8v. threshold levels input voltage threshold level combinations are indicat- ed by a two-letter code in the reset voltage threshold suffix guide (table 1). contact factory for availability of other voltage threshold combinations. reset outputs the max6715 max6729 provides an active-low reset output ( rst ) and the max6725/max6726 provides both an active-high (rst) and an active-low reset out- put ( rst ). rst, rst , rst1 , and rst2 are asserted when the voltage at either v cc 1 or v cc 2 falls below the voltage threshold level, rstin drops below threshold, or mr is pulled low. once reset is asserted it stays low for the reset timeout period (see table 2). if v cc 1, v cc 2, or rstin goes below the reset threshold before the reset timeout period is completed, the internal timer max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits _______________________________________________________________________________________ 9 pin description (continued) pin max6715/ max6716 max6717/ max6718 max6719/ max6720 max6721/ max6722 max6723/ max6724 max6725/ max6726 max6727 max6728/ max6729 name function 4 pfo active-low power-fail monitor output, open- drain or push-pull. pfo is asserted low when pfi is less than 0.626v. pfo deasserts without a reset timeout period. open- drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1. 4 rst active-high reset output, open-drain or push-pull. rst changes from low to high when v cc 1 or v cc 2 drops below selected reset thresholds, rstin is below threshold, mr is pulled low, or the watchdog triggers a reset. rst remains high for the reset timeout period after v cc 1/ v cc 2/rstin exceed the device reset thresholds, mr goes low to high, or the watchdog triggers a reset. open-drain outputs require an external pullup resistor. push-pull outputs are referenced to v cc 1.
max6715?ax6729 restarts. the max6715/max6717/max6719/max6721/ max6723/max6725/max6727/max6728 contain open- drain reset outputs, while the max6716/max6718/ max6720/max6722/max6724/max6726/max6729 contain push-pull reset outputs. the max6727 provides two separate open-drain rst outputs driven by the same internal logic. manual reset input many microprocessor-based products require manual reset capability, allowing the operator, a test techni- cian, or external logic circuitry to initiate a reset. a logic low on mr asserts the reset output. reset remains asserted while mr is low and for the reset timeout peri- od (t rp ) after mr returns high. this input has an internal 50k ? pullup resistor to v cc 1 and can be left uncon- nected if not used. mr can be driven with ttl or cmos logic levels, or with open-drain/collector outputs. connect a normally open momentary switch from mr to gnd to create a manual reset function; external debounce circuitry is not required. if mr is driven from long cables or if the device is used in a noisy environ- ment, connect a 0.1f capacitor from mr to gnd to provide additional noise immunity. adjustable input voltage the max6719/max6720 and max6723 max6727 provide an additional input to monitor a third system voltage. the threshold voltage at rstin is typically 626mv. connect a resistor-divider network to the circuit as shown in figure 1 to establish an externally controlled threshold voltage, v ext_th . v ext_th = 626mv((r1 + r2)/r2) low leakage current at rstin allows the use of large- valued resistors resulting in reduced power consump- tion of the system. watchdog input the watchdog monitors p activity through the watch- dog input (wdi). to use the watchdog function, con- nect wdi to a bus line or p i/o line. when wdi remains high or low for longer than the watchdog time- out period, the reset output asserts. leave wdi floating to disable the watchdog function. the max6721 max6729 include a dual-mode watch- dog timer to monitor p activity. the flexible timeout architecture provides a long period initial watchdog mode, allowing complicated systems to complete lengthy boots, and a short period normal watchdog mode, allowing the supervisor to provide quick alerts when processor activity fails. after each reset event (v cc power-up/brownout, manual reset, or watchdog reset), there is a long initial watchdog period of 35s minimum. the long watchdog period mode provides an extended time for the system to power-up and fully ini- tialize all p and system components before assuming responsibility for routine watchdog updates. the normal watchdog timeout period (1.12s min) begins after the first transition on wdi before the con- clusion of the long initial watchdog period (figure 2). during the normal operating mode, the supervisor will issue a reset pulse for the reset timeout period if the p does not update the wdi with a valid transition (high-to- low or low-to-high) within the standard timeout period (1.12s min). power-fail comparator pfi is the noninverting input to a comparator. if pfi is less than v pfi (626.5mv), pfo goes low. common uses for the power-fail comparator include monitoring prereg- ulated input of the power supply (such as a battery) or dual/triple ultra-low-voltage sot23 ? supervisory circuits 10 ______________________________________________________________________________________ max6719/ max6720/ max6723 max6727 v ext_th r1 r2 rstin gnd figure 1. monitoring a third voltage 1.12s max t wdi-normal 1.12s max t wdi-startup 35s max v th v cc wdi reset t rp figure 2. normal watchdog startup sequence
providing an early power-fail warning so software can conduct an orderly system shutdown. it can also be used to monitor supplies other than v cc 1 or v cc 2 by setting the power-fail threshold with a resistor-divider, as shown in figure 3. pfi is the input to the power-fail com- parator. the typical comparator delay is 2s from pfi to pfo . connect pfi to ground of v cc 1 if unused. ensuring a valid reset output down to v cc = 0 the max6715 max6729 are guaranteed to operate properly down to v cc = 0.8v. in applications that require valid reset levels down to v cc = 0 use a pull- down resistor at rst to ground. the resistor value used is not critical, but it must be large enough not to load the reset output when v cc is above the reset threshold. for most applications, 100k ? is adequate. this config- uration does not work for the open-drain outputs of the max6715/max6717/max6719/max6721/max6723/ max6725/max6727/max6728. for push-pull, active- high rst output connect the external resistor as a pullup from rst to v cc 1. applications information interfacing to ?s with bidirectional reset pins most microprocessors with bidirectional reset pins can interface directly to open-drain rst output options. systems simultaneously requiring a push-pull rst out- put and a bidirectional reset interface can be in logic contention. to prevent contention, connect a 4.7k ? resistor between rst and the p s reset i/o port as shown in figure 4. adding hysteresis to the power-fail comparator the power-fail comparator has a typical input hysteresis of 3mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (see the power-fail comparator section). if additional noise margin is desired, connect a resistor between pfo and pfi as shown in figure 5. select the values of r1, r2, and r3 so pfi sees v pfi (626mv) when v ext falls to its power-fail trip point (v fail ) and when vin rises to its power-good trip point (v good ). the hysteresis window extends between the specified v fail and v good thresholds. r3 adds the additional hysteresis by sinking current from the r1/r2 divider network when pfo is logic low and sourcing current into the network when pfo is logic high. r3 is typically an order of magnitude greater than r1 or r2. the current through r2 should be at least 2.5a to ensure that the 25na (max) pfi input current does not significantly shift the trip points. therefore, r2 < v pfi /2.5a < 248k ? for most applications. r3 will provide additional hysteresis for pfo push-pull (v oh = v cc 1) or open-drain (v oh = v pullup ) applications. max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits ______________________________________________________________________________________ 11 max6728/ max6729 r1 r2 pfi gnd v in pfo v trip = v pfi r1 + r2 r2 () max6728/ max6729 r1 r2 pfi gnd v cc v in pfo v trip = r2 (v pfi ) 1 r1 1 r2 +- v cc r1 [] () v pfi = 626.5mv a b figure 3. using power-fail input to monitor an additional power-supply a) v in is positive b) v in is negative max6715 max6729 gnd gnd v cc 1v cc 2 v cc 2 v cc 1 rst reset to other system components reset p 4.7k ? figure 4. interfacing to ?s with bidirectional reset i/o
max6715?ax6729 monitoring an additional power supply these p supervisors can monitor either positive or negative supplies using a resistor voltage-divider to pfi. pfo can be used to generate an interrupt to the p or cause reset to assert (figure 3). monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply voltage using the circuit shown in figure 3. when the negative supply is valid, pfo is low. when the negative supply voltage drops, pfo goes high. the circuit s accuracy is affected by the pfi threshold tolerance, v cc , r1, and r2. negative-going v cc transients the max6715 max6729 supervisors are relatively immune to short-duration negative-going v cc transients (glitches). it is usually undesirable to reset the p when v cc experiences only small glitches. the typical operating characteristics show maximum transient duration vs. reset threshold overdrive, for which reset pulses are not generated. the graph was produced using negative-going v cc pulses, starting above v th and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). the graph shows the maximum pulse width that a negative-going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. a 0.1f bypass capacitor mounted close to the v cc pin pro- vides additional transient immunity. watchdog software considerations setting and resetting the watchdog input at different points in the program, rather than pulsing the watch- dog input high-low-high or low-high-low, helps the watchdog timer to closely monitor software execution. this technique avoids a stuck loop where the watch- dog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 6 shows an exam- ple flow diagram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should hang in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. chip information transistor count: 1072 process: bicmos dual/triple ultra-low-voltage sot23 ? supervisory circuits 12 ______________________________________________________________________________________ max6728/ max6729 v ext r1 r3 r2 pfi gnd pfo a v good = desired v ext good voltage threshold v fail = desired v ext fail voltage threshold v oh = v cc 1 (for push-pull pfo) r2 = 200k ? (for > 2.5 a r2 current) r1 = r2 ((v good - v pfi ) - (v pfi )(v good - v fail ) / v oh ) / v pfi r3 = (r1 x v oh ) / (v good - v fail ) v good v fail v in pfo figure 5. adding hysteresis to power-fail for push-pull pfo start set wdi high program code subroutine or program loop set wdi low return subroutine completed hang in subroutine figure 6. watchdog flow diagram
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits ______________________________________________________________________________________ 13 functional diagram v cc 1 v ref v cc 2 rstin/pfi v ref v cc 1 mr v cc 1 v cc 1 v cc 1 reset timeout period v cc 2 rst rst pfo watchdog timer with float disable wdi v cc 1 mr pullup reset output driver v ref/2
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 14 ______________________________________________________________________________________ selector guide part number number of voltage monitors open- drain reset open- drain reset push- pull reset push- pull reset manual reset watch- dog input power- fail input/ output max6715 2 2 max6716 2 2 max6717 2 1 max6718 2 1 max6719 3 1 max6720 3 1 max6721 2 1 ? max6722 2 1 ? max6723 3 1 max6724 3 1 max6725 3 1 1 ? max6726 3 11 ? max6727 3 2 ? max6728 2 1 ? (open drain) max6729 2 1 ? (push-pull) ordering information (continued) part temp range pin-package max6721 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6722 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6723 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6724 ut_ _d_ -t -40 c to +85 c 6 sot23-6 max6725 ka_ _d_ -t -40 c to +85 c 8 sot23-8 max6726 ka_ _d_ -t -40 c to +85 c 8 sot23-8 max6727 ka_ _d_ -t -40 c to +85 c 8 sot23-8 max6728 ka_ _d_ -t -40 c to +85 c 8 sot23-8 max6729 ka_ _d_ -t -40 c to +85 c 8 sot23-8 note: the first ? _?are placeholders for the threshold voltage levels of the devices. desired threshold levels are set by the part number suffix found in the reset voltage threshold suffix guide. the ??after the d is a placeholder for the reset timeout delay time. desired delay time is set using the timeout period suffix found in the reset timeout period suffix guide. for example the max6716utltd3-t is a dual-voltage supervisor v th 1 = 4.625v, v th 2 = 3.075v, and 210ms (typ) timeout period.
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits ______________________________________________________________________________________ 15 table 1. reset voltage threshold suffix guide** part number suffix (_ _) v cc 1 nominal voltage threshold (v) v cc 2 nominal voltage threshold (v) lt 4.625 3.075 ms 4.375 2.925 mr 4.375 2.625 tz 3.075 2.313 sy 2.925 2.188 ry 2.625 2.188 tw 3.075 1.665 sv 2.925 1.575 rv 2.625 1.575 ti 3.075 1.388 sh 2.925 1.313 rh 2.625 1.313 tg 3.075 1.110 sf 2.925 1.050 rf 2.625 1.050 te 3.075 0.833 sd 2.925 0.788 rd 2.625 0.788 zw 2.313 1.665 yv 2.188 1.575 zi 2.313 1.388 yh 2.188 1.313 zg 2.313 1.110 yf 2.188 1.050 ze 2.313 0.833 yd 2.188 0.788 wi 1.665 1.388 vh 1.575 1.313 wg 1.665 1.110 vf 1.575 1.050 we 1.665 0.833 vd 1.575 0.788 table 2. reset timeout period suffix guide active timeout period timeout period suffix min [ms] max [ms] d1 1.1 2.2 d2 8.8 17.6 d3 140 280 d5 280 560 d6 560 1120 d4 1120 2240 ** standard versions are shown in bold and are available in a d3 timeout option only. standard versions require 2,500 piece order increments and are typically held in sample stock. there is a 10,000 order increment on nonstandard versions. other thresh- old voltages may be available, contact factory for availability.
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 16 ______________________________________________________________________________________ pin configurations gnd v cc 2 16 v cc 1 5 max6715/ max6716 sot23-6 top view 2 34 rst1 mr rst2 gnd v cc 2 16 v cc 1 5 max6721/ max6722 sot23-6 2 34 rst mr wdi gnd v cc 2 16 v cc 1 5 max6723/ max6724 sot23-6 2 34 rst wdi rstin 5 rstin gnd v cc 2 15 v cc 1 max6717/ max6718 sot23-5 2 34 rst mr gnd v cc 2 16 v cc 1 max6719/ max6720 sot23-6 2 34 rst mr v cc 2 mr rst 1 2 8 7 v cc 1 rstin gnd wdi rst sot23-8 3 4 6 5 max6725/ max6726 v cc 2 mr 1 2 8 7 v cc 1 rstin gnd wdi rst sot23-8 3 4 6 5 max6727 rst v cc 2 mr 1 2 8 7 v cc 1 pfi gnd wdi rst sot23-8 3 4 6 5 max6728/ max6729 pfo
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits ______________________________________________________________________________________ 17 package information sot5l.eps
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits 18 ______________________________________________________________________________________ package information (continued) 6lsot.eps
max6715?ax6729 dual/triple ultra-low-voltage sot23 ? supervisory circuits maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) sot23, 8l.eps

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